Advanced Digital Design and VLSI

This senior-level course delves into the advanced techniques and methodologies required for modern digital design and Very Large Scale Integration (VLSI). Students will gain a deep understanding of the entire design flow, from specification and architectural design using hardware description languages (HDLs) like SystemVerilog, through logic synthesis, simulation, verification, and ultimately physical implementation in FPGAs and ASICs. The course emphasizes practical application, equipping students with industry-relevant skills in timing analysis, power optimization, and design-for-testability, preparing them for careers in digital IC design and embedded systems. Beyond foundational concepts, the curriculum explores complex topics such as pipelining, memory interfaces, clock domain crossing, and advanced verification strategies including constrained random testing. Laboratory exercises will heavily utilize commercial Electronic Design Automation (EDA) tools for synthesis, place-and-route, and simulation, providing hands-on experience with real-world design challenges. The course culminates in a substantial final project where students design, implement, and verify a complex digital system, demonstrating their mastery of the complete digital design cycle and preparing them for advanced design roles.

Prerequisites

EET 210

Course outline

Lectures, virtual labs, and graded assignments — completed in your browser.

01Introduction to Advanced Digital Design and SystemVeriloglecture

02ASIC vs. FPGA Flows, Design Methodologies, and FSMslecture

03Combinational Logic Synthesis and Optimizationlecture

04Sequential Logic, Clocking, and Metastabilitylecture

05Pipelining, Data Paths, and Controller Designlecture

06Memory Architectures and Bus Protocolslecture

07Static Timing Analysis and Timing Closurelecture

08Midterm examassignment

09Power Estimation and Low-Power Design Techniqueslecture

10Clock Domain Crossing and Synchronizationlecture

11Advanced Verification Concepts and Methodologieslecture

12Design-for-Testability (DFT)lecture

13Physical Design: Place and Route Fundamentalslecture

14Final projectassignment

Syllabus

Course Objectives: Students will be able to design, simulate, synthesize, and verify complex digital systems using SystemVerilog; understand and apply modern VLSI design flows including synthesis, place-and-route, and timing closure; analyze and optimize designs for performance, power, and area; implement designs on FPGAs and comprehend ASIC design considerations; and utilize industry-standard EDA tools effectively.

Topics by Week:
Week 1: Introduction to Advanced Digital Design & SystemVerilog Refresher
Week 2: ASIC vs. FPGA Flows, Design Methodologies & FSM Design
Week 3: Combinational Logic Synthesis, Optimization & Delay Modeling
Week 4: Sequential Logic Synthesis, Clocking Strategies & Metastability
Week 5: Pipelining, Data Paths & Controller Design
Week 6: Memory Architectures, Interfaces & Bus Protocols
Week 7: Static Timing Analysis (STA) & Timing Closure Techniques
Week 8: Midterm Exam
Week 9: Power Estimation, Optimization & Low-Power Design Techniques
Week 10: Clock Domain Crossing (CDC) & Synchronization
Week 11: Introduction to Verification Methodologies (UVM concepts)
Week 12: Design-for-Testability (DFT): Scan Chains & BIST
Week 13: Physical Design: Place & Route, Layout Considerations
Week 14: Final Project Presentations

Grading Policy: Homework Assignments (20%), Lab Exercises (30%), Midterm Exam (20%), Final Project (30%). Active participation in discussions and labs is expected.